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sy89229u 1ghz precision, lvds 3, 5 clock divider with fail safe input and internal termination precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com augus t 2007 m9999-0 807 07-a hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89229u is a precision, low jitter 1ghz 3, 5 clock divider with an lvds output. a unique fail - safe input (fsi) protection prevents metastable output conditions when the input clock voltage swing drops significantly below 100m v or input is removed. the differential input includes micrel?s unique, 3 - pin internal termination architecture that allows the input to inte r face to any differential signal (ac - or dc - coupled) as small as 100mv (200mv pp ) without any level shifting or term in a tion resistor networks in the signal path. the ou t puts are 325mv, 100k - compatible lvds with fast rise/fall times guaranteed to be less than 220ps . the sy89229u operates from a 2.5v 5% supply and is guaranteed over the full industrial temper a ture range of ? 40c to +85c. the sy89229u is part of micrel?s high - speed, precision edge ? product line. all su p port documentation can be found on m i crel?s web site at: www.micrel.com . block diagram precision edge ? features ? accepts a high - speed input and provides a precision 3 and 5 sub - rate, lvds output ? fail - safe input ? prevents oscillations when input is invalid ? guaranteed ac performance over temperature and supply voltage: ? dc- to >1.0ghz throughput ? < 1500ps propagation delay (in - to - q) ? < 220ps rise/fall times ? ultra - low jitter design: ? <1ps rms random jitter ? <1ps rms cycle - to - cycle jitter ? <10ps pp total jitter (clock) ? <0.7ps rms mux crosstalk induced jitter ? unique patented internal termination and vt pin accepts dc - and ac - coupled inputs (cml, pecl, lvd s) ? wide input voltage range vcc to gnd ? 325mv lvds output ? 46% to 54% duty cycle( 3) ? 47% to 53% duty cycle( 5) ? 2.5v 5% supply voltage ? - 40c to +85c industrial temperature range ? available in 16 - pin (3mm x 3mm) qfn package applications ? fail - safe clock prot ection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 2 ordering information (1) part number package type operating range package marking lead finish SY89229UMG qfn -16 indu s trial 229u with pb - free bar - line indicator nipdau pb - free SY89229UMG tr (2) qfn -16 indu s trial 229u with pb - free bar - line indicator nipdau pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 16 - pin qfn
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 3 pin descr iption pin number pin name pin function 1, 4 in, /in differential input: this input pair is the differential signal input to the device, which accepts ac - or dc - coupled signal as small as 100mv. the input internally terminates to a vt pin through 50 ? and has level shifting resistors of 3.72 k ? to vcc. this allows a wide input voltage range from vcc to gnd. see figure 3, simplified differential input stage for details. note that this input will default to a valid (either high or low) state if left open. s ee ?input interface applications? subsection. 2 vt input termination center - tap: each side of the differential input pair terminates to the vt pin. the vt pin provides a center - tap for the input (in, /in) to a termination network for maximum interface fle xibility. see ?input interface applications? sub section for more details. 3 vref -ac reference voltage: this output biases to v cc ? 1.2v. it is used for ac - coupling inputs in and /in. connect vref - ac directly to the vt pin. bypass with 0.01f low esr capacit or to vcc. due to limited drive capability, the vref - ac pin is only intended to drive its respective vt pin. maximum sink/source current is 0.5ma. see ?input interface applications? subsection. 5 en single - ended input: this ttl/cmos - compatible input dis ables and enables the output. it is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. when disabled, q goes low and /q goes high. en being synchronous, outputs will be enabled/disabled after a rising and a falling edge of the input clock. v th = v cc /2. 6 /mr single - ende d input: this ttl/cmos - compatible input, when pulled low, asynchronously sets q output low and /q output high. note that this input is internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. v th = v cc /2. 7 nc no connect 8, 13 vcc positive power supply: bypass with 0.1 f in parallel with 0.01 f low esr capacitors as close to the v cc pins as possible. 12, 9 q, /q differential output: the output swing is typically 325mv. t he output must be terminated with 100 ? acro ss the pair (q, /q). see the ?truth table? below for the logic function. 10, 11, 14,15 gnd, exposed pad ground: ground and exposed pad must be connected to a ground plane that is the same potential as the ground pins. 16 div_sel single - ended input: this ttl/cmos - compatible input selects divide-by - 3 when pulled low and divide - by - 5 when pulled high. note that this input is internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. v th = v cc /2. truth table inputs outputs div_sel en /mr q /q x x 0 0 1 0 1 1 y 3 y 3 1 1 1 y 5 y 5 x 0 1 0 1
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 4 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input vo ltage (v in ) .................................. ? 0.5v to v cc lvds output current (i out )???????.10ma current (v t ) source or sink current on v t pin????100ma input current source or sink current on (in, /in) ........... 50ma current(v ref -ac ) source/sink current on v ref -ac (4) ............ 0.5ma maximum operating junction temperature?..125c lead temperature (soldering, 20 sec.) .......... +260c storage temperature (t s ) .................. ? 65c to 150c operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) qfn ( ja ) still - air ..................................................... 75 c/w qfn ( jb ) junction - to - board??????????.33c/w dc electrical characteristics (5) t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 2.5 2.625 v i cc power supply cu rrent no load, max v cc 52 68 ma r in input resistance (in -to -v t ) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 2a. note 6. 0.1 v cc v v diff_in differential input voltage swing |in - /in| see figure 2b. 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v ref - ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v v t_in voltage from input to v t 1. 8 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and fun c tional operation is not implied at conditions other than those detailed in the operational section s of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assum es exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still air unless otherwise stated. 4. due to limited drive capability use for input of the same package only. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 6. v in (max) is specified when v t is floating.
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 5 lvds outputs dc electrical characteristics (7) v cc = +2.5v 5%, r l = 100 across the outputs; t a = ? 40c to +85c, unless otherwise stated. symbol parameter conditi on min typ max units v out output voltage swing (q, /q) see figure 2a 250 325 mv v diff_out differential output voltage swing |q ? /q| see figure 2b 500 650 mv v ocm output common mode voltage (q, /q) see figure 5a 1.125 1.20 1.275 v ' v ocm change in common mode voltage (q, /q) see figure 5b ? 50 +50 mv lvttl/cmos dc electrical characteristics (7) v cc = 2.5v 5%; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 6 ac electrical characteristic s (8) v cc = 2.5v 5%; r l = 100 ? across the outputs; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units f max maximum input operating frequency v out 2 00mv 1.0 1.5 ghz tw minimum pulse width in, /in 400 ps t pd d ifferential propagation delay in -to -q 100mv < v in 200mv, note 9 900 1150 1500 ps in -to -q 200mv < v in 800mv, note 9 800 1050 1400 ps /mr(h -l) -to -q 350 530 800 ps t rr reset recovery time /mr(l -h) -to -in 400 ps t s en set - up time en -to -in note 10 300 ps t h en hold time in -to -en note 10 800 ps t skew part -to - part skew note 10 450 ps t jitter clock random jitter note 11 1 ps rms cycle -to - cycle jitter note 12 1 ps rms total jitter note 13 10 ps pp t r, t f output rise/fall time (20% to 80%) at full output swing. 100 220 ps output duty cycle( 3) duty cycle(input): 50%; f 1ghz; note 14 46 54 % output duty cycle( 5) duty cycle(input): 50%; f 1ghz; note 14 47 53 % notes: 8. high - frequency ac - parameters are guaranteed by design and characterization. 9. propagation delay is measured with input t r , t f 300ps (20% to 8 0%). the propagation delay is function of the rise and fall times at in. see ?typical operating characteristics? for details. 10. set - up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for asynchr onous applications, set - up and hold do not apply. 11. random jitter is measured with a k28.7 character pattern, measured at micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 7 functional description fail - safe input (fsi) the input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mv pk (200mv pp ), typically 30mv pk . maximum frequency of the sy89229u is limited by the fsi function. refer to figure 1b. input clock failur e case if the input clock fails to a floating, static, or extremely low signal swing, the fsi function will eliminate a metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under these con ditions. note that the fsi function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal as it nears the fsi threshold (typically 30mv). due to the fsi function, the propagation delay will depend on ris e and fall time of the input signal and on its amplitude. see ?typical operating characteristics? for detailed information. output duty cycle equation for a non 50% input, derate the spec by: for divide by 3 : (0.5 - 3 100 1 x + ) x100, in % for divide by 5 : (0.5 - 5 100 2 x + ) x100, in % x= input duty cycle, in % enable (en) en is a synchronous ttl/cmos - compatible input that enables/disables the outputs based on the input to wklv slq ,qwhuqdo n sxoo - up resistor defaults the in put to logic high if left open. input switching threshold is v cc /2. the enable function operates as follows: 1. the enable/disable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the inpu t clock when switching from en = low to en = high. however, when switching from en = high to en = low, the clock outputs will be disable d following an input clock rising edge and an output clock falling edge. 2. the enable/disable function always guarante es the full pulse width at the output before the clock outputs are disabled , non- depending on the divider ratio. refer to figure 1c for examples. divider operation the divider operation uses both the rising and falling edge of the input clock. for divide by 3, the falling edge of the second input clock cycle will determine the falling edge of the output. for divide by 5, the falling edge of the third input clock cycle. refer to figure 1d. example: if a 45% input duty cycle is applied or x=45, in divid e by 3 mode , the spec would expand by 1.67% to 44.3% - 55.7%
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 8 timing diagrams figure 1a. propagation delay figure 1b. fail safe feature
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 9 figure 1c. enable output timing diagram examples (divide by 3)
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 10 figure 1d. divider operation timing diagram
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 11 typical operating characteristics v cc = 2.5v, gnd = 0v, v in = 200mv, t r / t f 300ps, r l = 100 across the outputs; t a = 25c, unless otherwise stated.
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 12 functional characteristics v cc =2.5v, gnd = 0v, v in = 100mv, q = divide by 3, t r /t f 300ps, r l = 100 ? across the outputs; t a = 25c, unless otherwise stated.
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 13 single- ended and differential swings figure 2a. single - ended voltage swing figure 2b. differential voltage swing input stage figure 3. simplifi ed differential input stage
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 14 input interface applications figure 4a. lvpecl interface (dc - coupled) figure 4b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 4c. cml interface (dc - coupled) figure 4d. cml interface (ac -co upled) figure 4e. lvds interface (dc - coupled)
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 15 lvds output interface applications lvds specifies a small swing of 325mv typical, on a nominal 1.2v common mode above ground. the common mode voltage has tight limits to permit large variations in the gro und between and lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 5a. lvds differential measurement figure 5b. lvds common mode measurement related pr oduct and support documentation part number function datasheet link sy89228u 1ghz precision, lvpecl 3, 5 clock divider with fail safe input and internal termination http://www.micrel.com/_pdf/ hbw/sy89228u.pdf sy89230u 3.2ghz precision, lvpecl 3, 5 clock divider http://www.micrel.com/_pdf/hbw/sy89230u.pdf sy89231u 3.2ghz precision, lvds 3, 5 clock divider http://www.micrel.com/_pdf/hbw/sy89231u.pdf
micrel, inc. sy89229u augus t 2 007 m9999 -0 807 07 -a hbwhelp@micrel.com or (408) 955 - 1690 16 package information 16- pin qfn packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry - packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortun e drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal functi on of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be rea sonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or s ystems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages res ulting from such use or sale. ? 2007 micrel, inc.

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